Advance Computer Architectuer CS501 FALL 2010 second assignment solution

[Xpert]

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What will be the logic levels on the external SRC buses when each of the given SRC instruction is executing on the processor? Complete Table: A all numbers are in the decimal number system, unless noted otherwise. (Assume the required missing information if necessary). Also Specify memory addressing modes for each of the SRC instructions given in Table.

SRC instruction
RTL Equivalent
Address Bus<31….0>
Data Bus
<31….0>
MRead
MWrite
Addressing mode
Ld r9,4(r2)






Ld r4,4






Ld r3, M[r3]






Move r3, r2

Table: A

Assumptions:

• All memory content is aligned properly.
• In other words, all the memory accesses start at addresses divisible by 4.
• Value in the PC = 000DC348h

Memory map with assumed values


Register map with assumed values



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[noshaba bibi]

What will be the logic levels on the external SRC buses when each of the given SRC instruction is executing on the processor? Complete Table: A all numbers are in the decimal number system, unless noted otherwise. (Assume the required missing information if necessary). Also Specify memory addressing modes for each of the SRC instructions given in Table.SRC instruction
RTL Equivalent
Address Bus<31….0>
Data Bus
<31….0>
MRead
MWrite
Addressing mode

Ld r9,4(r2)


Ld r4,4

Ld r3, M[r3]
Move r3, r2

Table: A


Assumptions:

·1 All memory content is aligned properly.
·2 In other words, all the memory accesses start at addresses divisible by 4.
·3 Value in the PC = 000DC348h








Memory map with assumed values




Register map with assumed values

[noshaba bibi]

ap MCS k student ho???????

[Xpert]

i have completed my mcs.

[mc080402007]

Hi guys, where is the help/solution?

[cogent]

Hope it is a correct solution, it is my effort, But I could not fill all colmns so far. Do help me.
And[IMG]e://cs.jpg[/IMG] do not simply copy Paste,

May be I do not know how to attach a word document ? Hard Luck

[cogent]

SRC instruction RTL Equivalent Address Bus<31….0> Data Bus
just for reference.

<31….0> MRead MWrite Addressing mode
Ld r9,4(r2) R9 4xR2 Displacement
Ld r4,4 R4 M[4] Direct
Ld r3, M[r3] R3 M[R3] Register
Move r3, r2 R3 R2 unknown ???? 1 1 Register