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Thread: CS302- Digital Logic Design Assignment # 3 solution fall 2010

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    Bebo 32 CS302- Digital Logic Design Assignment # 3 solution fall 2010

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    Question_1: [marks: 14]
    The following serial data are applied to the flip-flop through the AND gates as indicated in figure below. Determine the resulting serial data that appear on the Q output. There is one clock pulse for each bit time. Assume that Q is initially 0 and that and are HIGH.
    Rightmost bits are applied first.


    J1: 1011110
    J2: 0101111
    J3: 0111110
    K1: 1100110
    K2: 0101110
    K3: 1101110



    Question_2: [marks: 6]
    Provide to-the-point (max 4 to 5 lines) answer to the following:

    • What is the main difference between a gated S-R latch and an edge-triggered S-R flip-flop?
    • How many flip-flops are required to produce a divide-by-32 device?


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  3. #2
    plz need solutions only first question i cant understand plz solve it

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    dear date is extend wait for the solution

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    my all dear in assignment mention make the wave form of 1st question then you get 7 mark
    and for making waveform study to lecture # 24 carefully and then prepare us assignment
    and one hint is that in assignment he said negative edge of clock pulse plz make it wave form according to -ve clock pulse then it is correct
    and no need to make any truth table of j-k flip flop and nor need to mention its output
    thanks aal dear be care to making assignment if any curry then discuses me on my id jamia07@skye about DLD only
    2- in 2nd question just make definition of ascronics and sysncronics filp-flop
    3- and in 3rd just make define its terms

  6. #5
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    Yar aap Sol send kro.......ok

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