Due DateView more random threads:
- CS402 Theory of Automata Assignment No.4 Fall 2012 Due Date...
- cs304 assignment no 2 fall 2011 solution required
- CS403 assignment no 5 fall 2010 solution on 29/01/2011
- CS403 Database Management Systems Assignment No.1 Solution...
- CS615 Software Project Management Assignment No.1 Solution...
- CS506 Assignment No 5 Solution requires January 2012
- CS506 assignment no 5 fall 2010 solution 29-01-2011
- CS604 Operating Systems solution assignment no 2 spring 2011
- CS201 Introduction to Programming Assignment No. 04...
- CS408 Human Computer Interaction Assignment No. 02 Semester...
Your assignment must be uploaded before or on 06th Jan 2011.
Upload Instructions
Please view the document related to assignment submission process provided to you by the Virtual University to upload the assignment.
Rules for Marking
Objective
This assignment has been designed to enable you to understand the concepts of:
Logic gates
Flip-flops
Latches
Assignment
Question_1: [marks: 14]
The following serial data are applied to the flip-flop through the AND gates as indicated in figure below. Determine the resulting serial data that appear on the Q output. There is one clock pulse for each bit time. Assume that Q is initially 0 and that and are HIGH.
Rightmost bits are applied first.
J1: 1011110
J2: 0101111
J3: 0111110
K1: 1100110
K2: 0101110
K3: 1101110
Question_2: [marks: 6]
Provide to-the-point (max 4 to 5 lines) answer to the following:
What is the main difference between a gated S-R latch and an edge-triggered S-R flip-flop?
How many flip-flops are required to produce a divide-by-32 device?
Sponsored Links
Urgent call: 03455242488. | Virtual University Assignments
Virtual University GDBs | Virtual University Papers | Vu Projects | Vu Handouts
About Expert
There are currently 1 users browsing this thread. (0 members and 1 guests)