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Thread: CS302- Digital Logic Design Assignment 3 solution fall 2010

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    Icon16 CS302- Digital Logic Design Assignment 3 solution fall 2010

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    Your assignment must be uploaded before or on 06th Jan 2011.
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    This assignment has been designed to enable you to understand the concepts of:
    Logic gates


    Question_1: [marks: 14]
    The following serial data are applied to the flip-flop through the AND gates as indicated in figure below. Determine the resulting serial data that appear on the Q output. There is one clock pulse for each bit time. Assume that Q is initially 0 and that and are HIGH.
    Rightmost bits are applied first.

    J1: 1011110
    J2: 0101111
    J3: 0111110
    K1: 1100110
    K2: 0101110
    K3: 1101110

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    Question_2: [marks: 6]
    Provide to-the-point (max 4 to 5 lines) answer to the following:
     What is the main difference between a gated S-R latch and an edge-triggered S-R flip-flop?
     How many flip-flops are required to produce a divide-by-32 device?
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