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    Thumbs up CS302 Digital Logic Design FINALTERM EXAMINATION SEMESTER FALL 2004

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    [COLOR="rgb(255, 0, 255)"]full paper in attachment [/COLOR]

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    Question No: 1 Marks: 8+8
    a) Convert each of the following POS expression to minimum SOP expression using a Karnaugh Map.
    b) Convert the decimal numbers 78 and 34 into Octal. Using octal addition, add the two numbers
    and convert the octal result back into decimal and verify the answer.
    Question No: 2 Marks: 8
    Draw the timing diagram of QA,QA , QB and QB . Assume the Positive edge triggering.
    It is required to construct a memory with 256 words, 16 bits per word. Cores are available in a
    matrix of 16 rows and 16 columns.
    a) How many matrices are needed?
    b) How many flip-flops are in the address and buffer registers?
    c) How many cores receive current during a read cycle?
    d) How many cores receive at least half-current during a write cycle?
    Question No: 5 Marks: 8
    Show the data output waveform for a 4-bit register with the parallel input data and the clock and
    SHIFT / LOAD waveform given in the figure. The serial data input (SER) is a 0. The parallel data
    inputs are D0=1, D1=0, D2=1, D3=0 as shown. Develop the data-output waveform in relation to the
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