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Thread: CS302 Digital Logic Design Assignment No 03 Spring June 2011

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    Icon51 CS302 Digital Logic Design Assignment No 03 Spring June 2011

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    Assignment No. 03
    Semester: Spring 2011
    CS302: Digital Logic Design

    Total Marks: 10
    Due Date: 08/06/2011

    Instructions:
    Please read the following instructions carefully before submitting assignment:
    It should be clear that your assignment will not get any credit if:

     The assignment is submitted after due date.
     The assignment is submitted via email.
     The submitted assignment does not open or file is corrupt.
     All types of plagiarism are strictly prohibited.

    Objectives:

    This assignment has been designed to enable you to understand the concepts of:

    Flip-Flops
    Flip-flops with asynchronous inputs
    Counters

    Guidelines:

    Perform/write all steps while solving the problems.
    Assignment


    Question No. 1 [Marks: 7]


    Determine Q output waveform for a negative edge triggered J-K flip-flop with preset, clear and J, K inputs. You are required to draw Q output waveform on timing diagram.



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    Question No. 2 [Marks: 1+2]

    Provide to-the-point answers to the following questions:

    a) How does a synchronous counter differ from asynchronous counter?
    b) How many states does a mod-12 counter have? What is minimum number of flip-flops required?
    Attached Files Attached Files

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    Last edited by Vuhelper; 06-06-2011 at 08:07 PM.

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    what about second question

  5. #4
    helper bhai ye to positive triggered hai assignment mein negative triggered hai
    so plz solve it again

  6. #5
    matlab harib???????
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  7. #6
    matlb ye ke assignment question mein humain negative triggered required hai positive nahi
    jabk ye positive edge triggered timing diagram hai

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    Icon16 cs302 discussion

    dear plz ap khud handouts ma sy flip- flop ka lecture read kro to ap ko is ki samjh aa jay gi k kis trah krni hy assignment or negitive triggerd ka matlab hy k clock pulse zero hy or agr clock pulse zero hy to NAND gate ko ik bhi zero O/P jay gi to wo logic 1 day ga just p is ma jahan bhi Q ki o/p hight hoti hy wahan change kr do

  9. #8
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    hurry up today is the last day to submit this assignment so please

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