## CS302- Digital Logic Design Assignment 4 SOLUTION (July 2010)

Assignment

Question_1: [marks: 6]
Two pulsed waveforms A and B are shown in figure below. Waveform A is leading waveform B in phase.

cs302.jpg

Suggest a flip-flop circuit to detect this condition by producing:
• a logic '1' Q output
• a logic '0' Q output

Question_2: [marks: 4]
Describe the main difference between a gated S-R latch and an edge-triggered S-R flip-flop.

cs302 1.jpg

Gated S-R latch mein EN use hota hai inputs ko enable krne k liye or an edge-triggered S-R flip-flop mein sath mein clock pulse bi use hota hai …..

Question_3: [marks: 10]
Determine the Q output for a negative edge-triggered J-K flip-flop for the input waveforms shown in the following figure. Assume that tH = 0 and Q = 0 initially.

cs302 2.jpg

truth table

cs302 3.jpg

1- AT CLOCK PULSE 2, J IS high AND k IS LOW,SO Q goes high set condition
2- AT CLOCK PULSE 4, J IS high AND k IS high,SO toggle condition,Q is Low
3- AT CLOCK PULSE 6, J IS high AND k IS high,SO again toggle condition,but this time Q goes high.
4- AT CLOCK PULSE 8 J IS high AND k IS high,SO here again toggle condition,and Q again changes so Q goes Low