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Thread: CS501 - Advance Computer Architecture Solved Quiz No 2 Discussion Fall 2014

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    CS501 - Advance Computer Architecture Solved Quiz No 2 Discussion Fall 2014

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    CS501 - Advance Computer Architecture Quiz No 2 Solution and Discussion Fall 2014 16th December 2014



    CS501 Advance Computer Architecture Solved Quiz

    Question # 1
    Where does the processor store the address of the first instruction of the ISR?
    Select correct option:
    =>Interrupt vector (p277)
    Interrupt request
    Interrupt handler
    All of the given options


    Question # 2
    In ________, a separate address space of the CPU is reserved for I/O operations.
    Select correct option:
    =>Isolated I/O (p236)
    Memory Mapped I/O
    All of above
    None of above


    Question # 3
    -------------- is the time needed by the CPU to recognize (not service) an interrupt request.
    Select correct option:
    =>Interrupt Latency (p279)
    Response Deadline
    Timer delay
    Throughput

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    Question # 4
    _________ is a technique in which some of the CPUs address lines forming an input to the address decoder are ignored.
    Select correct option:
    Microprogramming
    Instruction pre-fetching
    Pipelining
    =>Partial decoding (p255)


    Question # 5
    How can you define an interrupt?
    Select correct option:
    A process where an external device can speedup the working of the microprocessor
    A process where memory can speed up programs execution speed
    =>A process where an external device can get the attention of the microprocessor (p198, 223, 273)
    A process where input devices can takeover the working of the microprocessor


    Question # 6
    An interface that can be used to connect the microcomputer bus to ________is called an I/O Port.
    Select correct option:
    Flip Flops
    Memory
    =>Peripheral devices (p234)
    Multiplexers


    Question # 7
    Every time you press a key, an interrupt is generated. This is an example of
    Select correct option:
    =>Hardware interrupt
    Software interrupt
    All of the given
    None of the given


    Question # 8
    Identify the following type of serial communication error condition: The prior character that was received was not still read by the CPU and is over written by a new received character.
    Select correct option:
    Framing error
    Parity error
    =>Overrun error (p240)
    Under-run error


    Question # 9
    A software routine performed when an interrupt is received by the computer is called as ---------
    Select correct option:
    Interrupt
    =>Interrupt handler
    Exception
    Trap


    Question # 10
    Which one of the following methods for resolving the priority makes use of individual bits of a priority encoder?
    Select correct option:
    Daisy-Chaining Priority
    Asynchronous Priority
    =>Parallel Priority (p281)
    Semi-synchronous Priority


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    nstruction mul ra, rb, rc
    This instruction is only present in this processor and not in SRC. The first three steps are exactly same as of other instructions and would fetch the mul instruction. In step T3 we will bring the contents of register R [rb] in the buffer register A at the input of ALSU. In step T4 we take the multiplication of A with the contents of R[rc] and put it at the output of the ALSU in two registers C and CH. CH would contain the higher 16-bits while register C would contain the lower 16-bits. Now these two registers cannot transfer the data in one bus cycle to the registers, since the width is 16-bits. So we need to have 2 timing steps, in T5 we transfer the higher byte to register R[0] and in T6 the lower 16-bits are transferred to the placeholder R[a]. As a result of multiplication instruction we need 3 timing steps for Instruction Fetch and 4 timing steps for Instruction Execution and 7 steps altogether.

    mul.jpg
    div ra, rb, rc
    2.jpg

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